A direct conversion ADC or flash ADC has a comparator that fires for each decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range. Direct conversion is very fast, but usually has only 8 bits of resolution (256 comparators) or less, as it needs a large, expensive circuit. ADCs of this type have a large die size, a high input capacitance, and are
prone to produce glitches on the output (by outputting an out-of-sequence code). They are often used for video or other fast signals.
A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. The way successive approximation works is thru constantly comparing the input voltage to a known reference voltage until the best approximation is achieved. At each step in this process, a binary value of the approximation is stored in a successive approximation register (SAR).
The SAR uses a reference voltage (which is predetermined and reflects the conditions for which the ADC is used for) for comparisons. For example if the input voltage is 150V and the reference voltage is 100V, in the 1st clock cycle the voltage out is negative (in the sense that 100V is less than 150V). In the 2nd clock cycle the voltage might increase by say 30V (the increment being predetermined) to 130V. This
value is still negative. The 3rd clock cycle results in 160V, in which case the output is positive (as the output exceeds the input voltage). The result of this would be in the binary form 110. The 1ís refereeing to the times the voltage was negative and the 0ís referring to the positives (note in this case it is a 3-bit ADC, as the clock runs 3 times). This is also called bit-weighting conversion, and is similar to a binary search.
By increasing the number of bit cycles and decreasing the increment rise it is possible to construct an accurate ADC. ADCs of this type have good resolutions and quite wide ranges. They are more complex than some other designs.
A delta-encoded ADC has an up-down counter that feeds a digital to analogue converter (DAC). The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output is close enough to the input signal. The number is read from the counter. Delta converters have very wide ranges, and high resolution, but the conversion time is dependent on the input signal
level, though it will always have a guaranteed worst-case.
Delta converters are often very good choices to read real-world signals. Most signals from physical systems do not change abruptly. Some converters combine the delta and successive approximation approaches; this works especially well when high frequencies are known to be small in magnitude.
An integrating ADC produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters require the least number of transistors.
The ramp time is sensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter's value, or calibrate the timed ramp
A special advantage of the ramp-compare system is that comparing a second signal just requires another comparator, and another register to store the voltage value.